What makes something an emerging technology, and what makes it near-term? I asked this question of the IEDM technical committee at the press luncheon, because I had noticed in Kinam Kim’s talking points for his plenary talk that TSV was a separate line-item from emerging technologies. The response was that according to IEDM’s classification, an emerging technology was one that would not see commercialization for five years and beyond. John Suehle, NIST, moderator of the briefing, offered a tell-tale observation. “When you start to see reliability papers on a technology, you know it’s become a near term technology rather than emerging,” he explained. Based these two criteria, it’s safe to say that TSVs have officially made the leap from an emerging technology to a near term one.
In running through his selected list of noteworthy papers that the press should pay particular attention to, Suehle singled out only one involving 3D IC integration. Titled Investigation on TSV Impact on 65nm Devices and Circuits” and reporting on the combined work of Universitie of Savoie, CEA-Leti, and ST Microelectronics, it is the first study of electrical and mechanical impact of TSVs for 3D integration that looks at the impact of thermal mismatch between copper and silicon. “It’s one of the most comprehensive papers I’ve seen on the topic,” said Suehle. According to Patric Leduc, group leader for high density 3D integraton group at Leti who oversaw the work, the team was able to conclude that the thermal mismatch isn’t a problem for logic applications, and no keep out zone is required between the TSVs and transistors. (Research continues to evaluate impact on Analog chips).
This is great news for TSVs and logic applications… and yet, I couldn’t stop thinking; this was the ONLY noteworthy 3D paper at the event? Suehle elaborated for me. What makes a paper noteworthy by IEDM standards is that it offers some breakthrough technologies. Most of the other 3D presentations discussed incremental process improvements, which apparently isn’t a bad thing. “The fact that improvements are only incremental is a good sign. It means we’re closer to commercialization.” explained Zsolt Tokei , IMEC and IEDM subcommittee chair for characterization, reliability and yield.
The signs of TSVs progress are subtle, and if you’re not paying attention, you may miss them. For instance, you may notice, as I did, that the list of challenges (design tools, test, wafer thinning and handling, bonding processes, test) doesn’t change a whole lot, which to many would be a sign of stalled progress. But as I discussed with Tokei and Meikei Ieong, deputy director of the integration program at TSMC, It’s not what’s being said, it’s who’s saying it, and who’s addressing the challenges. Previously, it was the R&D guys, but now challenges are being addressed by the IDMs, design companies and test guys. Even standardization is being discussed and SEMI has formed a 3D stacked IC standards committee.
From Leti’s perspective, Leduc notes that 2 years ago there were lots of integration options. “We didn’t know what the solution for the application would be,” he says. “Today it’s clearer. By working closely with industry partners, we have more identified integration and are working with prototypes. We see tool suppliers more and more involved in 3D and interested in working with us.” What’s certain is that we’re getting closer. Leduc predicts that in 2 years we’ll see products.
I say we start planning the party now, because after all this, when TSV takes off, we’re going to want to celebrate. Who’s with me? – F.v.T.
