Last fall before SEMICON Europa, Andreas Ostmann, manager of the embedding and substrate technologies group, Fraunhofer IZM, spent some time with me explaining what he decribed as 3 distinct levels of 3D packaging. The first was die stacking through TSV. The second was what he termed a reconfigured wafer of molded single chips, citing as examples Freescale’s redistribution chip package (RCP), and the embedded wafer-level ball grid array, (eWLB) a collaborative effort of STATS ChipPAC, STMicrolectronics and Infineon. The third involves embedding chips into organic materials using PCB technologies. Ostmann’s own work at the Fraunhofer IZM, chip in polymer, via the Hiding Dies and Hermes programs, falls in this category.
In this third category, I’ve been following the work of a research group at Georgia Tech, who is developing an embedded 3D technology using liquid crystal polymer (LCP) as a base material. Due to its dielectric properties, flexibility, and near-hermetic nature, LCP can be used as a substrate, dielectric and sealant for 3D construction, making an all-LCP package a viable option. Swapan Bhattacharya and John Papapolymerou, of Georgia Tech’s School of Electrical and Computer Engineering have been leading this research, and have contributed a series of articles to Advanced Packaging magazine, outlining their work. Four of six parts have been published:
3D LCP Package Technologies Parts 1-4:
Part 1: Embedded Actives
Part 2: Laminated Thin Film Resistors on LCP
Part 3: Power Dividers on LCP
Part 4: Electroless Plated Thin-film Resistors on Organic Substrates
I’m looking forward to Parts 5 and 6, to round out the series. – F.v.T.
