A wise industry executive once told me (ok, it was Wilfried Bair, of SUSS MicroTec) that we would know when TSV was close to market adoption when the major players started considering it as viable option. By major players, he meant first-tier foundries, packaging houses, and device manufacturers. He makes a good point, because when you think about it, as important as it is for the equipment and materials suppliers to be ready with the necessary tools, processes, and chemistries, until a manufacturer shows interest, all those nifty innovations are just taking up space, waiting to be ordered. When someone offers such sage insight, I start watching for the signs. Several positive indicators popped up in the past few weeks, coincidentally out of Asia, a region that until now has been fairly quiet about its TSV programs.
Just last week, I learned of ASE’s plans to ramp up for post-fab processes for TSV manufacturing. ASE currently holds the number #1 position among the world’s semiconductor assembly test and packaging houses. And when #1 throws their hat in the ring, people sit up and take notice.
Then yesterday, a hot little item appeared in my inbox, courtesy of Lisa Lavin of STATS ChipPAC, about a new 3D TSV consortium being formed in Singapore as a collaborative effort of several state agencies and institutes. What’s most interesting is the line-up of participating companies — Chartered Semiconductor,STATS ChipPAC, and UTAC. There was also mention of leveraging materials and equipment suppliers to support the cause. To my knowledge, this is the first time major manufacturers themselves take up the gauntlet in a collaborative effort to accelerate market adoption of 3D ICs with TSVs. It seems as though the conundrum of who is going to do it, the front-end or back-end guys is being solved. As many predicted, it will be a combined effort with a combined goal of establishing an end-to-end TSV infrastructure in Singapore.
This announcement came on the heels of Elpida’s big news that it has completed development of a Cu-TSV multi-layer 8-Gigabit DRAM, and expect to ship samples at the end of 2009; with 16-Gigabit samples to follow in early 2010. Other applications earmarked for TSVs include high-density DRAM, memory/logic stacks and high-end graphics chips. According to a company statement, Elpida has installed a manufacturing line for TSV at the Hiroshima plant and will make use of Akita Elpida’s package processing to conduct full scale production in Japan. Nothing like a built-in infrastructure to move things along!
I asked Bob Patti, of Tezzaron Semiconductor, for his take on Elpida’s announcement, since Tezzaron is also in early production mode of DRAM memory using TSV interconnects. “I think the effort by Elpida is great. It is definitely a step forward in getting acceptance of 3D.” he said. He explained that Elpida’s TSVs are I/O level interconnect, therefore a 3D packaging approach. The stacking is similar to the technology Samsung showed with stacked flash, and represents some redesign of the memory. Samsung has also shown a 4 layer DRAM in the same vein. By comparison, Tezzaron’s memories interconnect with TSVs at the circuit level, which Patti says is a more radical approach resulting in better gains across more parameters. “Evolutionary vs. revolutionary” he calls it.
All this to illustrate that the stars are lining up for sure. A year ago, TSV was still considered by many to be destined only for niche applications. But the tides are turning, and the waves that started in R&D in Europe and the U.S. are lapping at Asian shores, closer than ever to market adoption.
