For the past two weeks, I’ve been slightly preoccupied with relocating from Massachusetts to Arizona. For much of that time, due to the drive across country and then subsequent delay in installing internet access at my new abode, I was disconnected from the internet and industry activities; needless to say, it’s a slightly unsettling feeling for an industry commentator. Today, FINALLY, I’m up and running once more, and catching up on news. It’s not surprising that while I’ve been on hiatus, organizations and companies devoted to developing 3D technologies have continued to make headlines. Let’s start out by recapping some of the highlights:
Just before I hit the road, Harvey Miller of IEEE contacted me about an upcoming event co-sponsored by IEEE Santa Clara Valley CPMT Society Chapter, and Electron Devices Chapter and Circuits and Systems Chapter titled “Through-Silicon Vias (TSVs): Design and Reliability” Sergey Savastiouk, ALLVIA, Inc. being held May 13, 2009 at the Biltmore Hotel in Santa Clara, CA. Savastiouk is a pioneer in TSV, and is responsible for coining the term itself. His expertise, therefore, encompasses the lifespan of this still emerging technology. With that deep a legacy, it should be iteresting to hear what he has to say about the design and reliability issues that have been identified as critical to market adoption.
Despite the state of the semiconductor industry as a whole, there continues to be optimistic news of growth coming out of the R&D sector, especially with regards to developments in 3D technologies. IMEC announced a 2,800m2 addition to its research facilities, to expand its research on, among other things, biomedical electronics. IMEC’s most recent 3D contribution in this area is the ultra-thin chip package. EV Group sold a photoresist developer,the EVG101D, to the University of Tokyo, continuing their success in the academic realm.
Collaboration continues to be the name of the game these days, with more announcements almost daily, such as Applied Materials and DISCO joining forces to jump on the wafer thinning bandwagon for TSV processes. Additionally, EVG and CEA Leti have entered into a joint development program involving EVG’s 300mm temporary bonding and debonding technologies. I’m curious to find out more about the connection between this and Leti’s JDP with Brewer Science. Look for more on the topic later this week.
Are the big design tool houses starting to pay more attention to design for 3D ICs? Phil Garrou’s coverage of an IEEE Components Packaging and Manufacturing Technology (CPMT) workshop in Austin, Texas alludes to Cadence’s involvement in that area. What I’m curious to find out is whether they’re referring to design for stacks interconnnected with wire bond or flip chip, or if they’ve addressed design for TSV integration yet.
So many questions yet to be answered! Count on me to find some answers. – F.v.T.
