When you’re totally immersed in any one topic, and therefore listen to nothing but presentations about novel processes, solutions, progress, innovations, equipment advancements on said topic for days at time, you start to hear A LOT of the same stuff over and over again. You assume everyone else has heard the same thing, until you realize that if this is their first presentation on said topic, they just might be hearing it for the first time. What appears repetitive and redundant to one person can still be completely new information to another.
I’ve listened to a slew of presentations throughout the course of my travels in the past month. Some contained information I’d heard repeatedly since I started following these technologies – such as “the technology drivers for 3D integration are form factor, increased performance and functionality, increased density, shorter interconnect, lower power consumption, reduced cost (when compared to scaling)…” and “target applications are CMOS image sensors (CIS) already in production, DRAM (coming soon), wireless applications, logic on memory stacks, and ultimately heterogeneous 3D systems.” I’m wondering, have these points been driven home yet? Even the presenters who come after previous presenters start skipping past those slides so as to not appear repetitive and redundant. Is it safe to say that the reasons for 3D integration are clear? Good – let’s move on to the next point then.
The latest 3D cause (for lack of a better term) I’ve been aware of, but I think is still unclear for those trying to grasp 3D is the hierarchy of 3D configurations. IMEC has been focusing on this for the past year or so, and Peter Ramm, Ph.D., director of the research program for system integration at the Fraunhofer IZM, talked about how he categorizes 3D during his talk Wednesday, at IMAPS 2009. He breaks it into two categories – configurations that use through-silicon vias, and those that don’t:
- 3D SiP – stacking packages or substrates
- 3D WLP – stacking of embedded die without TSV
Then when TSV is introduced, Ramm defines it as vertical systems integration, under which the categories are:
- 3D IC refers to stacking of transistor layers at local interconnect densities
- 3D SIC (stacked integrated circuit) refers to very high TSV densities interconnecting “blocks”.
- 3D SOC (system on chip) device stacking on global level for the fabrication of heterogeneous systems
Also attempting to clarify terminology was John Lau, from Hong Kong University of Science and Technology, who made a point several times during his discussion that he was referring to 3D IC Integration, NOT 3D Silicon Integration. It was the first time I’d heard that differentiator, but it’s intended to distinguish between low density TSVs and high-density TSVs.
During his IMAPS keynote address, Paul Franzon, professor of electrical and computer engineering at North Carolina State University, called these low-density TSVs coarse pitch TSVs for CIS and memory stacks; and referred to the high-density TSVs as the means for architectural optimization. Coarse TSVs are an advanced packaging process and high density TSVs are an advanced silicon integration process.
When you listen carefully, everyone is pretty much in agreement about what’s what, although the terms vary enough to cause some confusion. I’m in agreement with Peter Ramm that there’s a need to clarify all of this just to avoid confusion down the road. This is an area we’ll no doubt be revisiting and hearing about for some time.
Stay tuned for more observations on what’s happening in the exciting world of 3D technologies. Strong 3D tracks at both IMAPS and IWLPC the past two weeks provided me with enough to talk about at least until the next event, RTI ‘s 3D Systems Architecture for Semiconductor Integration and Packaging, December 8-11 in Burlingame, CA.
