The Ninth Annual Device Packaging Conference (DPC2013), held in Fountain Hills, AZ on March 11-14, 2013 is a major forum for the exchange of knowledge and provides numerous technical, social and networking opportunities for meeting leading experts in these fields. The conference will attract a diverse group of people within industry and academia. It provides a chance for educational interactions across many different functional groups and experience levels. People who will benefit from this conference include: scientists, process engineers, product engineers, manufacturing engineers, professors, students, business managers, sales and marketing.
The 2013 conference features technical sessions, panel discussions, a poster session, professional development courses and a vendor exhibition and a technology showcase focused on 2.5D and 3D IC and Packaging; Flip Chip and Wafer Level Packaging; MEMS and associated microsystems; and LED packaging.
On the 2.5D and 3D IC and packaging agenda are several keynotes, a panel and enough technology papers that it required a second devoted track on Thursday to cover them all. Some not-to-be missed 3D highlights include:
- Tuesday’s Keynote: 2.5 and 3D – Scaling Walls” is presented by Dr. Sitaram R. Arkalgud, VP of 3D Technology at Invensas Corporation, and formerly the director of the interconnect at SEMATECH. Arkalgud will examine some of the near term manufacturability concerns as well as key areas for 3D scaling, together with the electrical and thermo-mechanical challenges that accompany them.
- Wednesday’s Panel Discussion: 3D Integration – Applications and Production Challenges will feature such recognized 3D technology dignitaries as Sitaram Arkalgud, Invensas; Rich Rise, ASE US; Arif Rahman, Altera and Matt Nowak, Qualcomm. Come prepared to ask questions.
- Thursday Keynotes:
- 2.5 D Options: Organic Vs. Silicon.Vs Glass; Technologies, Costs and Applications, is presented by Dr. Rao R .Tummala, Director PRC Georgia Institute of Technology. Tummala will clarify the role and regimes of organic, silicon and glass interposers for 2.5 and 3D applications.
- Future of Package for Computing Electronics is presented by Ram S. Viswanath, Assembly Technology Planning and Pathfinding, INTEL CORPORATION. In his talk, Viswaneth will explain challenges and potential solutions associated with the increased demand for memory bandwidth, multi functionality, and higher wiring density to meet the Si scaling requirements, thinner and smaller form factors, multi-chip and embedded packaging while also addressing the challenges associated with demand for lower cost and environmental sustainability.
For more information and a complete agenda, visit www.imaps.org/devicepackaging
