At last week’s 3D Test Workshop in Anaheim, CA, I had the pleasure of moderating a panel of industry experts, analysts and bloggers, with a topic focused on 3D ICs, Hype vs. Reality? Jan Vardaman (TechSearch International), Herb Reiter (eda2asic) Paul Werbaneth (executive marketing consultant) and Ira Feldman (Feldman Engineering) joined me in the preparation and execution of what turned out to be a very lively discussion, with lots of participation from the attendees. In fact, I never even had to resort to my prepared questions.
Werbaneth established the framework for the discussion by explaining the concept of the hype cycle using the cast of the Big Bang Theory to illustrate his point (really, you had to be there). Essentially, every emerging technology goes through this cycle some make it, some don’t. The figure here explains it best. First there’s a technology trigger; in the case of 3D ICs it was the emergence of TSV technology. It rapidly climbed the curve to reach the “peak of inflated expectations” getting lots of press and attention on the semiconductor conference circuit. (Heck, even today, any topic with 3D ICs, TSVs 3D Packaging, or 2.5D packaging in the title is bound to fill a room). Then, as the expected adoption date was continually pushed out due to a laundry list of technology and logistical challenges (thin wafer handling, design tools, test, supply chain, yields, cost) 3D ICs plunged to the trough of disillusionment, which for some technologies is known as the Chasm of Death – from which there is no return. The technologies that make it through here, as 3D ICs seem to have, then go through the long slow climb known as the “slope of enlightenment” to reach the “plateau of productivity.”
After Werbaneth’s explanation, I queried both the attendees and the panel, where is 3D ICs on the hype cycle? The consensus is that 3D ICs are climbing out of the trough of disillusionment and starting the long, arduous climb up the slope of enlightenment. (I was slightly surprised by this – thinking we’re closer to the plateau of productivity based on the roadmaps of TSMC, Global Foundries and a number of the OSATS – but then again I tend to err on the side of optimism.) The key take-away from the Hype Cycle discussion is this: we’ve come to the point where real work is being done to overcome the remaining challenges of 3D ICs. We know that at some point, this technology will become critical to future needs, and therefore is well worth the investment to bring it to market.
The ensuing discussion focused mainly on two key questions posed by attendees. One was “Who do we need to convince to get this done?” Feldman provided his answer by describing a recent interaction he had with a colleague who works in a large data center. His (the data center guy’s) reaction to 3D ICs was that the technology seems great, but it’s nowhere near ready. He said they would never risk it until the reliability has been proven. This was a pretty significant encounter, in my opinion, since data centers have been pointed to as a key driver application to HVM. That was one strong dose of hype vs. reality.
However, I’m not sure we fully answered the question: who do we need to convince? The chip designers? The OEM manufactures? The fabless companies? At some point, someone will have to pull the trigger to put this ball in motion.
Another comment that garnered discussion was the need for capital infusion. Herb Reiter talked about recent discussions he’d had with Wall Street VC’s and how they are more interested in dumping money into social media start-ups than they are in 3D ICs at this point, because it’s a quick return on investment, while the 3D IC story lags on.
We also spent a good deal of time talking about the emerging supply chain models, and what we thought of TSMC’s intent to be the one stop shop. Here, Jan Vardaman and Herb Reiter disagreed. Vardaman has consistently voiced her concern about this model, and how since TSMC is not a memory manufacturer or supplier, its not going to be the preferred model for customers looking to manufacture wide I/O DRAM on logic devices. Reiter disagreed, and felt that many customers prefer TSMC’s approach because it takes care of the liability issue.
Now, here I have to add the disclaimer that it’s not easy to simultaneously moderate and editorially cover a panel. I did not take notes, so what you’ve read here is what glued itself to my memory. I’m hoping I got it mostly right, but I invite the panel to add their comments to this post to provide the full perspective. Also, please feel free to correct me if I quoted you in error! I look forward to continuing this discussion in the virtual space. To be continued… F.v.T.
