Sometimes there’s just a bunch of random stuff that catches my eye over the course of a week, and I set it aside until it gels into something that can be crafted into a topical curated piece. This is not one of those times. What we have here is a collection of important news in the 3D world that you should probably, if you haven’t already.
I read about PTI’s ramp of its logic IC backend business almost two weeks ago in Digitimes. This is significant because up until now, PTI has mostly served as an OSAT for the memory market. In the 3D space, PTI made headlines with its collaborative with UMC and Elpida to manufacture 3D ICs. But ever since Elpida filed bankruptcy last February, I’ve been waiting to hear what’s happening at PTI. According to this article, the controlling stake PIT acquired in Greatek Electronics has allowed them to adjust their product mix, decreasing their Memory (DRAM, NAND Flash) and increase their Logic IC business. Most interesting is the announcement of forward motion in their 3D IC products, with expected income from 3DIC to be generated in 2014.
Last week (September 25) Jedec standards group announced its specification for Synchronous DDR4, the first of its kind to include features supporting 3D stacking. EE Times’ Rick Merrit reports on it here. I believe this is a big step forward for 3D DRAM.
I’m sure that Tezzaron Semiconductor’s announcement about its acquisition of the assets of a semiconductor technology development and wafer fabrication facility in Austin, Texas previously run by SVTC Technologies on the heels of SVTC’s announcement that it intended to close the plant and lay off workers came as good news to those about to lose their jobs. Solid State Technologies’ Jim Montgomery (welcome back, Jim!) got the inside scoop about SVTCs initial troubles and Tezzaron’s intentions here. In any case, it sure looks like good things are happening at Tezzaron.
Shifting gears a bit to technology advancements (hey, I said it was a smorgasbord!). Tom Adams’ feature in the September issue of SST, Defect Detection in Die Stacks with Acoustic Imaging, is well worth a read. He talks about a simulation technique that reportedly “makes imaging easier and faster for stacked die and other multi-layered structures.” The technology was a collaborative effort of Sonoscan and the Technical University of Dresden. The article outlines the current challenges of using (acoustic micro imaging (AMI) in die stacks that are difficult to image acoustically due to the reflections caused by the layers. The simulation tool helps image individual layers of a stacked die sample. Here’s the whole story.
And since collaboration has become a vital message for the 3D value chain, I offer this insightful blog post by Global Foundries’ John Heinlein, which appears in The Foundry Files. In it, he compares the delivery of next-generation mobile devices with a layer cake, and uses a graphic that resembles die stacks more than cake to illustrate the need for collaboration of software, processor, graphics, system IP and physical IP. “Like a well-formed layer cake, the problem of delivering leading, next-generation mobile devices is not solved through any one component or technology. It takes a solution with all the layers of the stack working together.” He writes. Ok, I’ll by that analogy (and not just because I’m famished right now and cake sounds great.) ~ F.v.T.
