Due to extenuating circumstances, (Ok, truth: I’d just returned from a much needed 2 week vacation) I was unable to attend the GSA EDA 3D event at DAC in person last evening. But thanks to technology, I was able to participate via the live webcast and audio feed (isn’t virtual technology just the niftiest thing?) Since it was a cocktail event, I cracked open a beer, and settled into follow the webcast.
20 presentations in an hour and half… have you ever heard of speed dating? 5 or 10 minutes to make a first impression over cocktails before moving on to the next date. That’s what this was like – but in this case the presenters had 3-4 minutes to make their point. It went fast, and unfortunately I didn’t catch all the names of the speakers, but I got the gist of it. (So if I don’t mention you by name, but just by company, I apologize.)
2 thoughts – whoever implied the design community hasn’t been hard at work on developing 3D solutions was really uninformed. Either that, or these guys really know how to fly under the radar. Since mid-2009, the GSA’s EDA Interest Group, lead by Herb Reiter, has been focusing on emerging 3D/stacked die technology and the development of high productivity design tools to accelerate market acceptance for 3D. The main point that came across is that a good number of companies – from major design houses to smaller vendors – have made great strides in a relatively short period of time.
Here are some presentation tidbits I did catch. And I’ve been told the presentations and a recording of the evening will be made available on the GSA Website. There’s also a very comprehensive Tour Guide to 3D IC Design Tools and Services available there.
Herb Reiter set the stage, noting that the 3D community is really growing, requirements are challenging and we need to work together to succeed.
Pol Marchal, of IMEC, reported that the research institute is taking a system-level perspective, working on developing design rules for TSV, pathfinding and design tools, and working with the entire supply chain to develop an “industry-relevant solution”. So far, they have developed 5 3D test chips.
Ahmed Jeraya, of CEA Leti, explained that the “best” process depends on the application requirements. Therefore, Leti’s design flow includes 3D stack/package analysis and optimization and 3D implementation. “Today we are working on this with best in class EDA vendors to develop this design flow,” he noted. Among them, R3 Logic, and the recently announced common lab agreement with Docea, who has developed system-level design for optimizing power and thermal behavior.
The speaker from SEMI (was that John Ellis?) talked about the organizations work towards 3D standards. “We don’t want to standardize too early, because we’ll kill innovation,” he said, but it’s important to have a common nomenclature and common interfaces. Steve Schultz, of Si2 concurred, and said the company began working on developing standards for 3D design rules in 2009. He cited a design flow standards workshop with GSA, that focused on developing a dictionary of common terms, TSV modeling for required views and design steps, as well as infrastructure. The idea was to determine the essential modeling requirements for near-term applications, then move on to more challenging and advanced methods as they unfold.
Some of the major design houses weighed in reporting their progress in developing 3D IC tools. Cadence reported collaboration with EcoSystem – together they plan to bring a complete 3D solution to the marketplace that includes partitioning, floorplanning, etc.
On the test front, Mentor Graphics says they have available today, DRAM built-in-self-test (BIST) solutions available for 3D that includes interconnect test boundary scan, high speed channel test, and In-situ SOC test integrated into a flow. The company is looking to extend capabilities as they go. Additionally, Caliber is Mentor’s verification approach for 3D IC. It can support any model in simulation, and is suitable for current needs.
Synopsys’ Mark Williams also spoke of the company’s holistic approach for developing 3D tools, looking across all the tools in the company’s portfolio, and augmenting or adding in TSV-aware capabilities throughout suite of tools. He said Synopsys is working with larger IDM players as well as IMEC and TSMC on various 3D solutions.
MAGMA’s presenter cited Tezzaron’s Bob Patti’s reference to “bubble gum and scotch tape” meaning it’s possible to get products out the door with existing solutions, but with regard to how different layers are handled, verification, and lot of other things that we trivialize, it’s easy to make mistakes. It’s about EDA support, and Magma’s “unified data model” offers “true 3D support”.
The speaker identified as Mr. 3D (does that mean we’re related?) made his point with one slide, talking about an ecosystem for 3D design. He admonished not to forget the tech-tuning part, and that a simulation environment needs to be brought into the design flow.
John Sovinski, of CAD Design Solutions said the company is approaching 3D from a packaging point of view, extending packaging technology into stacking of TSVs. Companies want to see chips in every aspect of development and test. At CAD, a flow has been established, and can handle any type of packaging, circuit board and substrate. Additionally, it can link to all analysis software.
Bill Martin, of E-System Design, talked of the company’s signal and power integrity co-simulator, Sphinx, As well as a prototype tool for 3D extraction technology for wire bond and TSV that can analyze 50 – 100x more capacity than existing tools. E-System is working with CAD to complete the flow.
Gradient is working on tools for temperature simulation to avoid losing fine details in hotspots. Lorentz has a solution for adding electro-migration high speed IC design flow. EM design and synthesis is intergrated into the Cadence environment. Mark Mangum of MicroMagic, pioneers of the 3D layout editor with R3 Logic, says its tools are in the hands of 20 different design teams, actively used for 3D designs. He says data management is the biggest issue for 3D design. Kevin Reinbold, of Sigrity, told of the company’s work with 3D design and analysis, and its codesign tool for pad ring and system planning.
Reiter summed up the evening quite nicely: “We clearly need EDA vendors to provide modeling tools to manufacturers and design tools to the chip designers for manufacturing 3D ICs. We need to agree on and support establishing standards for these capabilities to make it possible to make tools efficiently.”
Like I said, it went fast, and I was drinking a beer, so if I got any of this wrong, feel free to post corrections, expand, and fill in the missing names. I won’t be offended. — F.v.T.
